MIT’s LEGO: A Compiler for AI Chips that Auto-Generates Fast, Efficient Spatial Accelerators

MIT researchers (Han Lab) launched LEGO, a compiler-like framework that takes tensor workloads (e.g., GEMM, Conv2D, consideration, MTTKRP) and routinely generates synthesizable RTL for spatial accelerators—no handwritten templates. LEGO’s entrance finish expresses workloads and dataflows in a relation-centric affine illustration, builds FU (purposeful unit) interconnects and on-chip reminiscence layouts for reuse, and helps fusing a number of spatial dataflows in a single design. The again finish lowers to a primitive-level graph and makes use of linear programming and graph transforms to insert pipeline registers, rewire broadcasts, extract discount bushes, and shrink space and energy. Evaluated throughout basis fashions and traditional CNNs/Transformers, LEGO’s generated {hardware} reveals 3.2× speedup and 2.4× power effectivity over Gemmini below matched assets.

Hardware Generation with out Templates

Existing flows both: (1) analyze dataflows with out producing {hardware}, or (2) generate RTL from hand-tuned templates with fastened topologies. These approaches limit the structure house and battle with fashionable workloads that must swap dataflows dynamically throughout layers/ops (e.g., conv vs. depthwise vs. consideration). LEGO straight targets any dataflow and combos, producing each structure and RTL from a high-level description quite than configuring a number of numeric parameters in a template.

Input IR: Affine, Relation-Centric Semantics (Deconstruct)

LEGO fashions tensor applications as loop nests with three index courses: temporal (for-loops), spatial (par-for FUs), and computation (pre-tiling iteration area). Two affine relations drive the compiler:

• Data mapping fI→Df_{I→D}: maps computation indices to tensor indices.
• Dataflow mapping fTS→If_{TS→I}: maps temporal/spatial indices to computation indices.

This affine-only illustration eliminates modulo/division within the core evaluation, making reuse detection and handle era a linear-algebra downside. LEGO additionally decouples management circulate from dataflow (a vector c encodes management sign propagation/delay), enabling shared management throughout FUs and considerably decreasing management logic overhead.

Front End: FU Graph + Memory Co-Design (Architect)

The primary aims is to maximise reuse and on-chip bandwidth whereas minimizing interconnect/mux overhead.

1. Interconnection synthesis. LEGO formulates reuse as fixing linear techniques over the affine relations to find direct and delay (FIFO) connections between FUs. It then computes minimum-spanning arborescences (Chu-Liu/Edmonds) to maintain solely needed edges (price = FIFO depth). A BFS-based heuristic rewrites direct interconnects when a number of dataflows should co-exist, prioritizing chain reuse and nodes already fed by delay connections to chop muxes and information nodes.
2. Banked reminiscence synthesis. Given the set of FUs that should learn/write a tensor in the identical cycle, LEGO computes financial institution counts per tensor dimension from the utmost index deltas (optionally dividing by GCD to cut back banks). It then instantiates data-distribution switches to route between banks and FUs, leaving FU-to-FU reuse to the interconnect.
3. Dataflow fusion. Interconnects for completely different spatial dataflows are mixed right into a single FU-level Architecture Description Graph (ADG); cautious planning avoids naïve mux-heavy merges and yields as much as ~20% power positive aspects in comparison with naïve fusion.

Back End: Compile & Optimize to RTL (Compile & Optimize)

The ADG is lowered to a Detailed Architecture Graph (DAG) of primitives (FIFOs, muxes, adders, handle turbines). LEGO applies a number of LP/graph passes:

• Delay matching by way of LP. A linear program chooses output delays DvD_v to decrease inserted pipeline registers ∑(Dv−Du−Lv)⋅bitwidthsum (D_v-D_u-L_v)cdot textual content{bitwidth} throughout edges—assembly timing alignment with minimal storage.
• Broadcast pin rewiring. A two-stage optimization (digital price shaping + MST-based rewiring amongst locations) converts costly broadcasts into ahead chains, enabling register sharing and decrease latency; a remaining LP re-balances delays.
• Reduction tree extraction + pin reuse. Sequential adder chains develop into balanced bushes; a 0-1 ILP remaps reducer inputs throughout dataflows so fewer bodily pins are required (mux as a substitute of add). This reduces each logic depth and register depend.

These passes concentrate on the datapath, which dominates assets (e.g., FU-array registers ≈ 40% space, 60% energy), and produce ~35% space financial savings versus naïve era.

Outcome

Setup. LEGO is carried out in C++ with HiGHS because the LP solver and emits SpinalHDL→Verilog. Evaluation covers tensor kernels and end-to-end fashions (AlexNet, MobileNetV2, ResNet-50, EfficientNetV2, BERT, GPT-2, CoAtNet, DDPM, Stable Diffusion, LLaMA-7B). A single LEGO-MNICOC accelerator occasion is used throughout fashions; a mapper picks per-layer tiling/dataflow. Gemmini is the principle baseline below matched assets (256 MACs, 256 KB on-chip buffer, 128-bit bus @ 16 GB/s).

End-to-end velocity/effectivity. LEGO achieves 3.2× speedup and 2.4× power effectivity on common vs. Gemmini. Gains stem from: (i) a quick, correct efficiency mannequin guiding mapping; (ii) dynamic spatial dataflow switching enabled by generated interconnects (e.g., depthwise conv layers select OH–OW–IC–OC). Both designs are bandwidth-bound on GPT-2.

Resource breakdown. Example SoC-style configuration reveals FU array and NoC dominate space/energy, with PPUs contributing ~2–5%. This helps the choice to aggressively optimize datapaths and management reuse.

Generative fashions. On a bigger 1024-FU configuration, LEGO sustains >80% utilization for DDPM/Stable Diffusion; LLaMA-7B stays bandwidth-limited (anticipated for low operational depth).

Importance for every section

• For researchers: LEGO supplies a mathematically grounded path from loop-nest specs to spatial {hardware} with provable LP-based optimizations. It abstracts away low-level RTL and exposes significant levers (tiling, spatialization, reuse patterns) for systematic exploration.
• For practitioners: It is successfully hardware-as-code. You can goal arbitrary dataflows and fuse them in a single accelerator, letting a compiler derive interconnects, buffers, and controllers whereas shrinking mux/FIFO overheads. This improves power and helps multi-op pipelines with out handbook template redesign.
• For product leaders: By reducing the barrier to customized silicon, LEGO allows task-tuned, power-efficient edge accelerators (wearables, IoT) that maintain tempo with fast-moving AI stacks—the silicon adapts to the mannequin, not the opposite approach round. End-to-end outcomes in opposition to a state-of-the-art generator (Gemmini) quantify the upside.

How the “Compiler for AI Chips” Works—Step-by-Step?

1. Deconstruct (Affine IR). Write the tensor op as loop nests; provide affine f_{I→D} (information mapping), f_{TS→I} (dataflow), and management circulate vector c. This specifies what to compute and how it’s spatialized, with out templates.
2. Architect (Graph Synthesis). Solve reuse equations → FU interconnects (direct/delay) → MST/heuristics for minimal edges and fused dataflows; compute banked reminiscence and distribution switches to fulfill concurrent accesses with out conflicts.
3. Compile & Optimize (LP + Graph Transforms). Lower to a primitive DAG; run delay-matching LP, broadcast rewiring (MST), reduction-tree extraction, and pin-reuse ILP; carry out bit-width inference and non-obligatory energy gating. These passes collectively ship ~35% space and ~28% power financial savings vs. naïve codegen.

Where It Lands within the Ecosystem?

Compared with evaluation instruments (Timeloop/MAESTRO) and template-bound turbines (Gemmini, DNA, MAGNET), LEGO is template-free, helps any dataflow and their combos, and emits synthesizable RTL. Results present comparable or higher space/energy versus professional handwritten accelerators below comparable dataflows and applied sciences, whereas providing one-architecture-for-many-models deployment.

Summary

LEGO operationalizes {hardware} era as compilation for tensor applications: an affine entrance finish for reuse-aware interconnect/reminiscence synthesis and an LP-powered again finish for datapath minimization. The framework’s measured 3.2× efficiency and 2.4× power positive aspects over a number one open generator, plus ~35% space reductions from back-end optimizations, place it as a sensible path to application-specific AI accelerators on the edge and past.

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